Power management of chips that contain a single processing module by adjusting the system clock frequency is a well-known technique used by designers of portable, battery-operated computing equipment such as laptop computers, handheld computers, cell phones, etc. The system clock can be adjusted downward or upward to match the processing requirements of the applications that are currently running. Since there is only one processing module, the system clock frequency can be optimized solely for its requirements.
On a multi-processor system where the system clock is shared amongst multiple processing elements, the determination of the optimal system clock frequency is not so straightforward.
One approach is to simply run the system clock at its maximum frequency and gate off the clock source to individual processing elements when they are idle. This approach saves the power that would be consumed by an idle processing element. However, a significant portion of the power used by a particular chip design may actually be consumed by chip components other than the processor cores. Leaving the system clock running at a high frequency causes these overhead components to continue to drain power at a higher rate than is necessary.
So, it is desirable to be able to reduce the frequency of a shared clock to the minimum frequency that allows the processing elements to function correctly while using the least amount of power.
Examples of applications where such a control feature would be desirable include:                A chip that contains two or more CPU cores, all of which share a common system clock.        An on-chip bus that hosts two or more bus masters, all of which share a common bus clock.        